Fault modeling and worst-case test vectors of sequential ASICs exposed to total dose
AA Abou-Auf, MM Abdel-Aziz… - … on Nuclear Science, 2012 - ieeexplore.ieee.org
We introduce a novel methodology for identifying worst-case test vectors for sequential
circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use …
circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use …
Fault modeling and worst-case test vectors for delay failures induced by total dose in ASICs
AA Abou-Auf, MM Abdel-Aziz… - … on Nuclear Science, 2012 - ieeexplore.ieee.org
We analyzed the delay failure induced in standard-cell ASICs by total-ionizing dose. We
developed a novel cell-level fault model for delay failures. We used this fault model to …
developed a novel cell-level fault model for delay failures. We used this fault model to …
A comprehensive comparison between design for testability techniques for total dose testing of flash-based FPGAs
MA Ibrahim, MM Abdel-Aziz… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
A comprehensive comparison between different design for testability (DFT) techniques for
total-ionizing-dose (TID) testing of flash-based field-programmable gate arrays (FPGAs) is …
total-ionizing-dose (TID) testing of flash-based field-programmable gate arrays (FPGAs) is …
Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques
MS Abdelwahab - 2018 - fount.aucegypt.edu
Electronic devices often operate in harsh environments which contain a variation of radiation
sources. Radiation may cause different kinds of damage to proper operation of the devices …
sources. Radiation may cause different kinds of damage to proper operation of the devices …
Identifying Worst-Case Test Vectors for Delay Failures Induced by Total Dose in Flash-based FPGA
A Ammar - 2015 - fount.aucegypt.edu
A thesis presented on the effects of space radiation on the flash-based FPGA leading to
failure with applying a proposed fault model to identify the worst, nominal and best-case test …
failure with applying a proposed fault model to identify the worst, nominal and best-case test …
Worst-case test vectors of sequential ASiCS exposed to total dose
AA Abou-Auf, MM Abdel-Aziz… - 2011 12th European …, 2011 - ieeexplore.ieee.org
We introduce a novel methodology for identifying worst-case test vectors for sequential
circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use …
circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use …