Modeling DVFS and power-gating actuators for cycle-accurate NoC-based simulators

D Zoni, W Fornaciari - ACM Journal on Emerging Technologies in …, 2015 - dl.acm.org
Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to
support the multi-core revolution. One of the major design issues of multicore architectures is …

A dvfs cycle accurate simulation framework with asynchronous noc design for power-performance optimizations

D Zoni, F Terraneo, W Fornaciari - Journal of Signal Processing Systems, 2016 - Springer
Abstract Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-
cores, with a strong influence on the performance of the whole chip. On-chip network affects …

Generating concurrent test-programs with collisions for multi-processor verification

A Adir, G Shurek - … High-Level Design Validation and Test …, 2002 - ieeexplore.ieee.org
We discuss collisions that are of interest to multiprocessor verification. Collisions occur when
different processes access a shared resource. We investigate how the results of such …

Sensor-wise methodology to face NBTI stress of NoC buffers

D Zoni, W Fornaciari - 2013 Design, Automation & Test in …, 2013 - ieeexplore.ieee.org
Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from
the performance and reliability stand-points. Unfortunately, continuous scaling of CMOS …

A control-based methodology for power-performance optimization in nocs exploiting dvfs

D Zoni, F Terraneo, W Fornaciari - Journal of Systems Architecture, 2015 - Elsevier
Abstract Networks-on-Chip (NoCs) are considered a viable solution to fully exploit the
computational power of multi-and many-cores, but their non negligible power consumption …

Optimizing thin client caches for mobile cloud computing: Design space exploration using genetic algorithms

AHA Badawy, G Yessin, V Narayana… - Concurrency and …, 2017 - Wiley Online Library
The emergence and rapid spread of interest and use of cloud computing as an accessible
and expandable, as needed, computing facility on the go, has a very deep affinity to the …

A cycle accurate simulation framework for asynchronous noc design

F Terraneo, D Zoni, W Fornaciari - … International Symposium on …, 2013 - ieeexplore.ieee.org
Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for
current and future multi-cores. In such a scenario power represents a major design obstacle …

Runtime resource management for embedded and HPC systems

W Fornaciari, G Pozzi, F Reghenzani… - Proceedings of the 7th …, 2016 - dl.acm.org
Resource management is a well known problem in almost every computing system ranging
from embedded to High Performance Computing (HPC) and is useful to optimize multiple …

Online inertia-based temperature estimation for reliability enhancement

M Chhablani, I Koren… - Journal of Low Power …, 2016 - ingentaconnect.com
With the advent of technology scaling and the increased use of high performance multi-
cores in life-critical applications, reliability has become an increasingly pressing issue. High …

Nbti-aware design of noc buffers

D Zoni, W Fornaciari - Proceedings of the 2013 Interconnection Network …, 2013 - dl.acm.org
Network-on-Chips (NoC) play a central role in determining performance and reliability in
current and future multi-core architectures. Continuous scaling of CMOS technology enable …