Optimized buffer protection for network-on-chip based on Error Correction Code
Newest technologies of integrated circuits manufacture require a communication
architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple …
architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple …
Partial evaluation based triple modular redundancy for single event upset mitigation
S Katkoori, SA Islam, S Kakarla - Integration, 2021 - Elsevier
We present a design technique, Partial evaluation-based Triple Modular Redundancy
(PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic …
(PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic …
[PDF][PDF] Review on Fault-Tolerant NoC Designs
By benefiting from the development of the semiconductor technology, many-core System-on-
Chips (SoCs) have been widely used in electronic devices. Network-on-Chips (NoCs) can …
Chips (SoCs) have been widely used in electronic devices. Network-on-Chips (NoCs) can …
Multiple fault mitigation in network-on-chip architectures through a bit-shuffling method
R Mercier - 2021 - theses.hal.science
Since several decades, fault tolerance has become a major research field due to transistor
shrinking and power scaling in system-on-chips. Especially, faults occurring to Network-on …
shrinking and power scaling in system-on-chips. Especially, faults occurring to Network-on …
[PDF][PDF] Evaluation of fault tolerance in network on chip: fault injection and performance analysis between different fault protection schemes
L Temmel - 2019 - scholar.archive.org
Network on Chip is a communication system used in integrated circuits as an alternative to
bus systems. Instead of all chip elements exchanging their data directly or via a bus, packets …
bus systems. Instead of all chip elements exchanging their data directly or via a bus, packets …