A 32 nm single-ended single-port 7T static random access memory for low power utilization

B Rawat, P Mittal - Semiconductor Science and Technology, 2021 - iopscience.iop.org
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

B Rawat, P Mittal - International Journal of circuit theory and …, 2021 - Wiley Online Library
Static random access memory (SRAM) bit cell is a prominent element for portable devices.
The popularity of sleek designs and demand for longer battery life has driven memory cell …

A reliable and temperature variation tolerant 7T SRAM cell with single bitline configuration for low voltage application

B Rawat, P Mittal - Circuits, Systems, and Signal Processing, 2022 - Springer
Static random access memory is a key component for most microprocessor-based digital
devices. With the declining technology node and reducing supply voltage, it is essential to …

LCNT-an approach to minimize leakage power in CMOS integrated circuits

R Lorenzo, S Chaudhury - Microsystem Technologies, 2017 - Springer
Leakage power dissipation is the dominant contributor of total power dissipation in
nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS …

Adaptive technique for overcoming performance degradation due to aging on 6T SRAM cells

R Faraji, HR Naji - IEEE Transactions on device and materials …, 2014 - ieeexplore.ieee.org
The threshold voltage drifts induced by positive bias temperature instability (PBTI) and
negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These …

Comparative analysis of the design techniques for low leakage SRAMs at 32nm

M Gupta, K Gupta, N Pandey - Microprocessors and Microsystems, 2021 - Elsevier
This paper presents a comprehensive overview of leakage reduction techniques prevailing
in Static Random Access Memories (SRAMs) by classifying them in three categories namely …

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

A Beg - International Journal of Circuit Theory and Applications, 2015 - Wiley Online Library
This paper presents an automatic method for sizing the transistors in CMOS gates. The
method utilizes a feedback control system to efficiently optimize the transistor sizes in small …

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

D Albano, M Lanuzza, R Taco… - International Journal of …, 2015 - Wiley Online Library
Gate‐level body biasing provides an attractive solution to increase speed and robustness
against process and temperature variations while maintaining energy efficiency. In this …

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

B Ebrahimi, R Asadpour… - … Journal of Circuit …, 2015 - Wiley Online Library
In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged
bitlines is presented. By using the strained pMOS transistor technology, the degradation of …

Efficiency improvement of integrated synchronous buck converter using body biasing for ultra-low-voltage applications

R Faraji, H Farzanehfard, E Adib - Microelectronics Journal, 2017 - Elsevier
This article presents an integrated synchronous DC-DC buck converter for ultra-low-voltage
and low-power applications with 200 mV–1 V input and 100 mV–500mV output in 45 nm …