IC quality and test transparency

EJ McCluskey, F Buelow - IEEE Transactions on Industrial …, 1989 - ieeexplore.ieee.org
It is shown that extremely high single-stuck fault coverage is necessary for high-quality
products. Even 100% single-stuck fault coverage may not guarantee adequate quality …

High-yield assembly of multichip modules through known-good IC's and effective test strategies

JK Hagge, RJ Wagner - Proceedings of the IEEE, 1992 - ieeexplore.ieee.org
Multichip module technology has been shown to offer significant improvements for
electronics equipment in the areas of miniaturized size, reduced weight, capability for higher …

Test sets and reject rates: All fault coverages are not created equal

PC Maxwell, RC Aitken - IEEE Design & Test of Computers, 1993 - ieeexplore.ieee.org
The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data
from a part tested with both functional and scan tests are analyzed and compared with …

Built-in self-test trends in Motorola microprocessors

RG Daniels, WC Bruce - IEEE Design & Test of Computers, 1985 - ieeexplore.ieee.org
The first built-in self-test feature in a Motorola sidered a" wart" until a RAM test application
recast it as a" feature." Though the BIST approach-an idea conceived as a way to reduce …

CrossCheck: A cell based VLSI testability solution

T Gheewala - 26th ACM/IEEE Design Automation Conference, 1989 - ieeexplore.ieee.org
A new testability solution is proposed in which externally accessible test points are pre-
designed into cells that comprise the VLSI designs. The test points are accessed through an …

An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited

DV Das, SC Seth, PT Wagner… - Proceedings …, 1990 - ieeexplore.ieee.org
The authors report on an experiment to verify the accuracy of reject ratio predictions by the
available approaches. The data collection effort includes instrumenting the wafer probe test …

An observability enhancement approach for improved testability and at-speed test

EM Rudnick, V Chickermane… - IEEE transactions on …, 1994 - ieeexplore.ieee.org
Some recent studies show that an at-speed sequential or functional test is better than a test
executed at lower speed. Design-for-testability approaches based on full scan, partial scan …

A participant's perspective

RG Daniels - IEEE Micro, 1996 - ieeexplore.ieee.org
Presents the history of the microprocessor as told by an active participant. The author looks
at the state of the computer industry before 1970, and how this led into the beginning of …

Testability features of the SuperSPARC microprocessor

R Patel, K Yarlagadda - Proceedings of IEEE International Test …, 1993 - ieeexplore.ieee.org
The Texas Instruments SuperSPARC is a high performance BiCMOS superscalar
microprocessor containing 3.1 M transistors. This paper describes the testability features of …

Correlating defect level to final test fault coverage for modular structured designs/spl lsqb/microcontroller family/spl rsqb

TJ Powell, KM Butler, M Ales, R Haley… - Proceedings of IEEE …, 1994 - ieeexplore.ieee.org
The Texas Instruments TMS370 is in volume production. Sample manufacturing data has
been collected to correlate stuck fault grades to the defect levels that would have been …