[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments

J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …

A tutorial and review of automobile direct ToF LiDAR SoCs: evolution of next-generation LiDARs

K Yoshioka - IEICE Transactions on Electronics, 2022 - search.ieice.org
LiDAR is a distance sensor that plays a key role in the realization of advanced driver
assistance systems (ADAS). In this paper, we present a tutorial and review of automotive …

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power

D Tasca, M Zanuso, G Marzin… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …

A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier

KS Kim, YH Kim, WS Yu, SH Cho - IEEE Journal of Solid-State …, 2013 - ieeexplore.ieee.org
In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate,
and programmable gain for a wide input range. Using the proposed pulse-train time …

A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register

KS Kim, WS Yu, SH Cho - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …

A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC

A Elkholy, T Anand, WS Choi, A Elshazly… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …

A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2 ps

P Lu, A Liscidini, P Andreani - IEEE journal of solid-state …, 2012 - ieeexplore.ieee.org
Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-
digital converter (TDC), where the already small quantization noise of the standard Vernier …

A 0.6-V 13-bit 20-MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques

M Zhang, CH Chan, Y Zhu… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-
assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this …

A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications

H Liu, D Tang, Z Sun, W Deng… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …

An 8-bit 10-GS/s 16× interpolation-based time-domain ADC with< 1.5-ps uncalibrated quantization steps

M Zhang, Y Zhu, CH Chan… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves 10
GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0 …