Tolerating permanent faults in the input port of the network on chip router
Deep submicron technologies continue to develop according to Moore's law allowing
hundreds of processing elements and memory modules to be integrated on a single chip …
hundreds of processing elements and memory modules to be integrated on a single chip …
TSV-OCT: A scalable online multiple-TSV defects localization for real-time 3-D-IC systems
In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and
operating phases, most of the existing methods use a dedicated testing mechanism with …
operating phases, most of the existing methods use a dedicated testing mechanism with …
Light-weight spiking neuron processing core for large-scale 3D-NoC based spiking neural network processing systems
With the increasing demand for computing machines that more closely model the biological
brain, the field of neuro-inspired computing has progressed to the exploration of Spiking …
brain, the field of neuro-inspired computing has progressed to the exploration of Spiking …
Efficient optimization and hardware acceleration of cnns towards the design of a scalable neuro inspired architecture in hardware
Convolution Neural Networks (CNNs) are responsible for the major discoveries in image
classification and they are considered as the core of most current computer vision systems …
classification and they are considered as the core of most current computer vision systems …
A non-blocking non-degrading multiple defects link testing method for 3D-networks-on-chip
As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs),
Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However …
Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However …
2D Parity Product Code for TSV online fault correction and detection
Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D
Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the …
Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the …
2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults
Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D
Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the …
Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the …
Thermal distribution and reliability prediction for 3D Networks-on-Chip
As one of the most promising technologies to reduce footprint, power consumption and wire
latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for …
latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for …
A two‐dimensional RC network topology for fault‐tolerant design of analog circuits
HM Paiva, RKH Galvao, S Hadjiloucas… - … Journal of Circuit …, 2022 - Wiley Online Library
This paper proposes a novel one‐port passive circuit topology consisting of a two‐
dimensional network of resistors and capacitors, which can be used as a fault‐tolerant …
dimensional network of resistors and capacitors, which can be used as a fault‐tolerant …
Architecture and Design Methodology for Highly-Reliable TSV-NoC Systems
NK Dang, AB Abdallah - 2018 - eprints.uet.vnu.edu.vn
During the past few decades, a lot of research has been focusing on Three-dimensional
Networks-on-Chips (3D-NoCs) as an auspicious solution to alleviate the interconnect …
Networks-on-Chips (3D-NoCs) as an auspicious solution to alleviate the interconnect …