Toward a multiple clock/voltage island design style for power-aware processors
E Talpes, D Marculescu - … on Very Large Scale Integration (VLSI …, 2005 - ieeexplore.ieee.org
Enabled by the continuous advancement in fabrication technology, present-day
synchronous microprocessors include more than 100 million transistors and have clock …
synchronous microprocessors include more than 100 million transistors and have clock …
Dynamically trading frequency for complexity in a gals microprocessor
S Dropsho, G Semeraro, DH Albonesi… - … (MICRO-37'04), 2004 - ieeexplore.ieee.org
Microprocessors are traditionally designed to provide" best overall" performance across a
wide range of applications and operating environments. Several groups have proposed …
wide range of applications and operating environments. Several groups have proposed …
Interconnected rings and oscillators as gigahertz clock distribution nets
MS Maza, ML Aranda - Proceedings of the 13th ACM Great Lakes …, 2003 - dl.acm.org
The performance of interconnected rings and oscillators, working as clock distribution
networks, is analyzed and compared among several configurations. The use of …
networks, is analyzed and compared among several configurations. The use of …
A critical analysis of application-adaptive multiple clock processors
E Talpes, D Marculescu - … of the 2003 international symposium on Low …, 2003 - dl.acm.org
Enabled by the continuous advancement in fabrication technology, present day
synchronous microprocessors include more than 100 million transistors and have clock …
synchronous microprocessors include more than 100 million transistors and have clock …
Dynamic capacity-speed tradeoffs in smt processor caches
Caches are designed to provide the best tradeoff between access speed and capacity for a
set of target applications. Unfortunately, different applications, and even different phases …
set of target applications. Unfortunately, different applications, and even different phases …
Computational neurobiology meets semiconductor engineering
D Hammerstrom - … on Multiple-Valued Logic (ISMVL 2000), 2000 - ieeexplore.ieee.org
Many believe that the most important result to come out of the last ten years of neural
network research is the significant change in perspective in the neuroscience community …
network research is the significant change in perspective in the neuroscience community …
Analysis and verification of interconnected rings as clock distribution networks
MS Maza, ML Aranda - Proceedings of the 14th ACM Great Lakes …, 2004 - dl.acm.org
The use of interconnected rings approach, as globally asynchronous, locally synchronous
clock distribution network, offers good performance regarding scalability, low clock-skew …
clock distribution network, offers good performance regarding scalability, low clock-skew …
[图书][B] Multiple clock domain microarchitecture design and analysis
GP Semeraro - 2003 - search.proquest.com
As clock frequency increases and feature size decreases, clock distribution and skew
tolerance present growing challenges to the designers of singly-clocked, globally …
tolerance present growing challenges to the designers of singly-clocked, globally …
The REMAP reconfigurable architecture: A retrospective
The goal of the REMAP project was to gain new knowledge about the design and use of
massively parallel computer architectures in embedded real-time systems. In order to …
massively parallel computer architectures in embedded real-time systems. In order to …
Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor
G Semeraro, DH Albonesi, S Dropsho… - Workshop on …, 2003 - infoscience.epfl.ch
Microprocessors are traditionally designed to provide “best overall” performance across a
wide range of applications and operating environments. Several groups have proposed …
wide range of applications and operating environments. Several groups have proposed …