Embedded vision systems: A review of the literature
Over the past two decades, the use of low power Field Programmable Gate Arrays (FPGA)
for the acceleration of various vision systems mainly on embedded devices have become …
for the acceleration of various vision systems mainly on embedded devices have become …
A reconfigurable multiple transform selection architecture for VVC
Video coding plays an important role in the highly information-based world as videos
contribute the largest part of network traffic. The latest video coding standard Versatile Video …
contribute the largest part of network traffic. The latest video coding standard Versatile Video …
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K
Y Omori, T Onishi, H Iwasaki… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper describes a new 120 fps (frames per second) real-time HEVC (High Efficiency
Video Coding) encoder for HFR (high frame rate) video encoding and transmission. HFR …
Video Coding) encoder for HFR (high frame rate) video encoding and transmission. HFR …
Design and implementation of an efficient multi-pattern motion estimation search algorithm for HEVC/H. 265
S Gogoi, R Peesapati - IEEE Transactions on Consumer …, 2021 - ieeexplore.ieee.org
Motion Estimation (ME) is the most computationally intensive block in high efficiency video
coding (HEVC) due to its complex partition schemes. It consumes a large amount of power …
coding (HEVC) due to its complex partition schemes. It consumes a large amount of power …
A single-chip 4K 60-fps 4: 2: 2 HEVC video encoder LSI employing efficient motion estimation and mode decision framework with scalability to 8K
T Onishi, T Sano, Y Nishida, K Yokohari… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
A professional-image-quality video encoder LSI for broadcasting and content distribution
has been developed with single-chip 4K 60-fps 4: 2: 2 high-efficiency video coding (HEVC) …
has been developed with single-chip 4K 60-fps 4: 2: 2 high-efficiency video coding (HEVC) …
High-performance carry select adders
R Jothin, P Sreelatha, A Ahilan… - Circuits, Systems, and …, 2021 - Springer
This research article proposes high-performance square-root carry select adder (SQRT
CSLA) architectures with high speed, area and energy efficiency when compared to the …
CSLA) architectures with high speed, area and energy efficiency when compared to the …
Hardware implementation for the HEVC fractional motion estimation targeting real-time and low-energy
This paper presents an energy-aware and high-throughput hardware design for the
Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) …
Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) …
Efficient compression-based line buffer design for image/video processing circuits
H Wang, T Wang, L Liu, H Sun… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Line buffer is a typical and major on-chip memory design architecture for image/video
processing circuits. As it usually occupies very large on-chip circuit area, it is of great …
processing circuits. As it usually occupies very large on-chip circuit area, it is of great …
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding
The sum of absolute difference (SAD) calculation is one of the most computing-intensive
operations in video encoders compatible with recent standards, such as high-efficiency …
operations in video encoders compatible with recent standards, such as high-efficiency …
Low-power and memory-aware approximate hardware architecture for fractional motion estimation interpolation on HEVC
Nowadays, current video coding standards like the High Efficiency Video Coding (HEVC)
implement several complex coding tools, like the Fractional Motion Estimation (FME). An …
implement several complex coding tools, like the Fractional Motion Estimation (FME). An …