In this survey, we review several approaches for predicting performance of Network-on-Chip
(NoC)-based multicore systems, starting from the traffic models to the complex NoC models …

With continuing miniaturization, NoCs with 1024 nodes will become realistic around the year
2020. The design of such NoCs requires efficient simulation techniques to evaluate design …

As the number of processing elements in modern chips keeps increasing, the evaluation of
new designs will need to account for various challenges at the NoC level. To cope with the …

A scalable asynchronous NoC router with lower power consumption and latency comparing
to a synchronous design is introduced in this article. It employs GALS interfaces …

We evaluate the applicability of many-core architectures for the simulation of networks on
chips (NoC). Compared to the well established shared memory multi-core architectures …

State-of-the-art parallel systems employ a huge number of computing nodes that are
connected by an interconnection network. An interconnection network (ICN) plays an …

This work presents the development of a Network-on-Chip environment based on multiagent
systems. This simulator aims to provide high level of abstraction to quickly simulate …

Interconnection network (ICN) has been playing an important role in parallel systems, since
it greatly affects the system-level organization as well as its inherent communication …

Last level cache management and core interconnection network play important roles in
performance and power consumption in multicore system. Large scale chip multicore uses …

Integrated systems have incorporated a variety of functionalities within the same chip,
requiring on-chip communication mainly based on the Network-on-Chip (NoC) design …