The pursuit of accurate diagnosis with good resolution is driven by yield learning during both
early bring-up and production excursions. Unfortunately, fault callouts from diagnosis tools …

Fault diagnosis methodologies for analog circuits lag far behind those for their digital
counterparts. In this paper, we show how the generic Symmetry-based Built-In Self-Test …

Oftentimes fault candidates produced by logic diagnosis are too many to effectively guide
the follow-on failure analysis. In this work, we propose a novel two-stage fast screening …

Emerging devices are susceptible to manufacturing defects due to immature fabrication
processes. Ferroelectric field-effect transistors, referred to as FeFETs, are promising …

In this paper, an environment for modeling scenarios and processes in intelligent agriculture
settings, known as ViSMod, is presented. ViSMod is developed as an expert system the …

We discuss the state-of-the-art on fault diagnosis for analog circuits with a focus on
techniques that leverage machine learning. For a chip that has failed either in post …

Abstract Machine learning (ML) has been used in logic-circuit diagnosis for over a decade.
Many different types of ML have been deployed including, support vector machine, decision …

Designers have to be prepared for the scenario where chips do not work as intended or do
not meet performance expectations after they are fabricated. Product yield engineers need …

The number of integrated circuits (ICs) used in safety-and mission-critical applications is
ever increasing. These applications demand that ICs carry functional safety properties. In …

Due to the perturbations inherent to integrated circuit (IC) fabrication, an immature or
problematic process may systematically introduce defects that significantly reduces yield …