Asynchronous NoC with Fault tolerant mechanism: A Comprehensive Review
R Siddagangappa - 2022 Trends in Electrical, Electronics …, 2022 - ieeexplore.ieee.org
The Network on Chip (NoC) is a cost-effective alternative to bus-based connectivity in most
multi-core networks. The NoC system solves the drawbacks of bus-based networks by …
multi-core networks. The NoC system solves the drawbacks of bus-based networks by …
Butterfly pitch-angle distributions observed by ISEE-1
TA Fritz, M Alothman, J Bhattacharjya… - Planetary and Space …, 2003 - Elsevier
The ISEE-1 satellite has observed butterfly pitch-angle distributions (PAD) in protons and
electrons from 20 keV to 2 MeV in the low latitude outer magnetosphere, which showed a …
electrons from 20 keV to 2 MeV in the low latitude outer magnetosphere, which showed a …
Asynchronous-Logic QDI quad-rail sense-amplifier half-buffer approach for NoC router design
We propose a low area overhead and power-efficient asynchronous-logic quasi-delay-
insensitive (QDI) sense-amplifier half-buffer (SAHB) approach with quad-rail (ie, 1-of-4) data …
insensitive (QDI) sense-amplifier half-buffer (SAHB) approach with quad-rail (ie, 1-of-4) data …
Scalable and power-efficient implementation of an asynchronous router with buffer sharing
C Effiong, G Sassatelli… - … Euromicro Conference on …, 2017 - ieeexplore.ieee.org
Network-on-Chip provides scalable communication in Systems-on-Chip with many
Intellectual Property cores. Studies have shown that unutilized router buffers lead to …
Intellectual Property cores. Studies have shown that unutilized router buffers lead to …
A Minimal Buffer Router with Level Encoded Dual Rail‐Based Design of Network‐on‐Chip Architecture
T Patil, A Sandi, DM Deepak Raj… - Wireless …, 2022 - Wiley Online Library
Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic
power consumption, modularity, heterogeneous nature, and robustness to the process …
power consumption, modularity, heterogeneous nature, and robustness to the process …
Configurable network-on-chip router macrocells
S Saponara, L Fanucci - Microprocessors and Microsystems, 2016 - Elsevier
This paper presents a configurable architecture for Network-on-Chip (NoC) router
macrocells, and a methodology to streamline their design and configuration. The …
macrocells, and a methodology to streamline their design and configuration. The …
A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems
Q Zeng, J Wang, J Cong, D Shang - IEEE Access, 2024 - ieeexplore.ieee.org
In multi-core heterogeneous systems, communication on the data bus/NoC (Network-on-
Chip) is complex. To ensure low-latency transmission of high-level messages, such as …
Chip) is complex. To ensure low-latency transmission of high-level messages, such as …
A highly efficient dynamic router for application-oriented network on chip
N Su, H Gu, K Wang, X Yu, B Zhang - The Journal of Supercomputing, 2018 - Springer
With the number of processor cores increasing in chip multiprocessors, the network on chip
becomes a reliable structure with its perfect parallel communication performance. The …
becomes a reliable structure with its perfect parallel communication performance. The …
[PDF][PDF] 基于“包-电路” 交换的双环片上网络设计
李桢旻， 马宇晴， 殷海文， 杜高明， 王晓蕾… - 电子测量与仪器 …, 2023 - jemi.cnjournals.com
针对包交换片上网络(NoC) 在大量数据通信情况下性能较差的弱点, 提出了一种基于“包-
电路”(PCC) 交换的环形拓扑结构片上网络(DRNoC) 设计架构. 首先这种双环形拓扑结构由内外 …
电路”(PCC) 交换的环形拓扑结构片上网络(DRNoC) 设计架构. 首先这种双环形拓扑结构由内外 …
异步2D-Torus 片上网络自适应路由算法
李贞妮， 李晶皎， 方志强， 王骄 - 东北大学学报(自然科学版), 2015 - xuebao.neu.edu.cn
采用异步电路设计方法学, 针对确定性路由算法在异步片上网络实现中遇到的容易阻塞和路由
资源浪费等问题, 提出了一种适用于2D-Torus 拓扑结构的异步片上网络自适应路由算法 …
资源浪费等问题, 提出了一种适用于2D-Torus 拓扑结构的异步片上网络自适应路由算法 …