A delay model for static CMOS gates with application in gate level logic simulation is
presented. It incorporates the degradation effect on narrow pulses and is named PID (pure …

While delay modeling of gates with a single switching input has received considerable
attention, the case of multiple inputs switching in close temporal proximity is just beginning …

Static timing analysis has traditionally used the PERT method for identifying the critical path
of a circuit. The authors show in this paper that due to the influence of the transition time of a …

This book provides the reader with an extensive background in the field of logic-timing
simulation and delay modeling. It includes detailed information on the challenges of logic …

As semiconductor manufacturing has entered into nanoscale era, performance degradation
due to Negative Bias Temperature Instability (NBTI) became one of the major threats to …

The time-of-flight based ranging mechanism defined in 802.11-2016 offers a range of
parameters too rich to be implemented with similar pattern among vendors, unless further …

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital
simulation. The model combines the degradation delay model presented in previous papers …

Timing characterization of standard cells is one of the essential steps in VLSI design. The
traditional static timing analysis (STA) tool assumes single input switching models for the …

This contribution extends the Degradation Delay Model (DDM), previously developed for
CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all …

Indoor location remains challenging. GPS and cellular signals do not alwayspenetrate
buildings well, and legacy techniques that relied in Wi-Fi broadcasts have lost their luster …