Despite advances in the programmable logic capabilities of modern trigger systems, a
significant bottleneck remains in the amount of data to be transported from the detector to off …

In harsh radiation environments, nanoscale CMOS latches have become more and more
vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can …

In the harsh space environment, the phase-locked loop (PLL) circuit is vulnerable to
radiation effects, which will lead to performance degradation or even function interrupts. In …

In a spacecraft, flip-flops take part in holding operational configuration for long durations.
Single event transients (SETs) at control inputs of such flip-flops can culminate in single …

Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates Page 1
Abstract—Transistor reordering and insertion of decoupling cells are explored to reduce the …

Novel design techniques for efficient testability are developed and have been implemented
in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this …

Exposure to high-energy particles leads to a potential risk of generating single-event
transients (SETs) in active devices of microelectronic circuits, compromising signal integrity …

This article investigates the single-event effects on 16-nm bulk field-effect transistors
(FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation …

Since there are many uncertain factors in the generation and propagation of single event
transient (SET), it is a very important issue that how to quantify the impact of these uncertain …

This paper evaluates the potential of using the sleep transistor in FinFET logic cells to
mitigate the process variability effects and the soft error susceptibility. The insertion of a …