One of the most important industrial applications of SAT is currently Bounded Model
Checking (BMC). This technique is typically used for formal hardware verification in the …

We describe Btor2, a word-level model checking format for capturing models of hardware
and potentially software in a bit-precise manner. This simple, line-based and easy to parse …

In recent years, researchers have developed a number of tools to conduct taint analysis of
Android applications. While all the respective papers aim at providing a thorough empirical …

Symbolic model checking is an important tool for finding bugs (or proving the absence of
bugs) in modern system designs. Because of this, improving the ease of use, scalability, and …

We report on the last four editions of the reactive synthesis competition (SYNTCOMP 2018–
2021). We briefly describe the evaluation scheme and the experimental setup of …

Incremental SAT is about solving a sequence of related SAT problems efficiently. It makes
use of already learned information to avoid repeating redundant work. Also preprocessing …

We present AVR, a push-button model checker for verifying state transition systems directly
at the source-code level. AVR uses information embedded in the word-level syntax of the …

Increasing demand on computer networks continuously pushes manufacturers to
incorporate novel features and capabilities into their switches at an ever-accelerating pace …

While bit-level IC3-based algorithms for hardware model checking represent a major
advance over prior approaches, their reliance on propositional clause learning poses …

In this paper, we revisit and formalize temporal decomposition, as one of the most basic,
widely-used and effective preprocessing techniques in hardware model checking. The main …