Ultra deep reactive ion etching of high aspect-ratio and thick silicon using a ramped-parameter process

Y Tang, A Sandoughsaz, KJ Owen… - Journal of …, 2018 - ieeexplore.ieee.org
This paper reports an advanced deep reactive ion etching (DRIE) process for realizing ultra-
deep (500-μm) and ultra-high aspect-ratio (UHAR) silicon structures (AR 40 for 1-mm …

Towards the fabrication of high-aspect-ratio silicon gratings by deep reactive ion etching

Z Shi, K Jefimovs, L Romano, M Stampanoni - Micromachines, 2020 - mdpi.com
The key optical components of X-ray grating interferometry are gratings, whose profile
requirements play the most critical role in acquiring high quality images. The difficulty of …

Fabrication of high aspect ratio micro-structures with superhydrophobic and oleophobic properties by using large-area roll-to-plate nanoimprint lithography

N Atthi, M Dielen, W Sripumkhai, P Pattamang… - Nanomaterials, 2021 - mdpi.com
Bio-inspired surfaces with superamphiphobic properties are well known as effective
candidates for antifouling technology. However, the limitation of large-area mastering …

Fabrication of robust PDMS micro-structure with hydrophobic and antifouling properties

N Atthi, W Sripumkhai, P Pattamang… - Microelectronic …, 2020 - Elsevier
Because of its flexibility, when polydimethylsiloxane (PDMS) is fabricated as a biomimetic
antifouling surface, the surface micro-structure is usually vulnerable to structural collapse …

Sea of electrodes array (SEA): extremely dense and high-count silicon-based electrode array technology for high-resolution high-bandwidth interfacing with 3D neural …

AS Zardini, B Rostami, K Najafi, VL Hetrick, OJ Ahmed - Biorxiv, 2021 - biorxiv.org
In this work, we propose a new silicon-based micro-fabrication technology to fabricate 3D
high-density high-electrode-count neural micro-probe arrays scalable to thousands and …

[图书][B] Nanoelectronics: Device physics, fabrication, simulation

J Knoch - 2020 - books.google.com
The author presents all aspects, in theory and experiments, of nanoelectronic devices
starting from field-effect transistors and leading to alternative device concepts such as …

Thin-piezo on single-crystal silicon reactive etched RF MEMS resonators

A Zaman, A Alsolami, IF Rivera, J Wang - IEEE Access, 2020 - ieeexplore.ieee.org
This paper demonstrates how a single crystal silicon wafer can be used to fabricate thinfilm
piezoelectric-on-silicon (TPoS) resonators by utilizing a modified version of Single Crystal …

Three-dimensional simulation of DRIE process based on the narrow band level set and monte carlo method

JC Yu, ZF Zhou, JL Su, CF Xia, XW Zhang, ZZ Wu… - Micromachines, 2018 - mdpi.com
A three-dimensional topography simulation of deep reactive ion etching (DRIE) is developed
based on the narrow band level set method for surface evolution and Monte Carlo method …

Analytics-statistics mixed training and its fitness to semisupervised manufacturing

P Parashar, CH Chen, C Akbar, SM Fu, TS Rawat… - PloS one, 2019 - journals.plos.org
While there have been many studies using machine learning (ML) algorithms to predict
process outcomes and device performance in semiconductor manufacturing, the extensively …

Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers

M Wietstruck, S Marschmeyer, M Lisker… - 2017 IEEE 67th …, 2017 - ieeexplore.ieee.org
In this work, the development of engineered silicon substrates for a novel via-middle TSV
integration concept is demonstrated. These substrates include 3D buried etch-stop layers …