Ferroelectric field effect transistors (FeFETs): advancements, challenges and exciting prospects for next generation non-volatile memory (NVM) applications

J Ajayan, P Mohankumar, D Nirmal… - Materials Today …, 2023 - Elsevier
Data intensive applications such as AI (Artificial Intelligence) and IoT (Internet of Things)
demand high performance and highly reliable non-volatile memories (NVM). FeFET offers …

A Ge-channel ferroelectric field effect transistor with logic-compatible write voltage

D Das, PV Ravindran, C Park… - IEEE Electron …, 2022 - ieeexplore.ieee.org
A major roadblock for the integration of ferroelectric-field-effect transistors (FEFETs) at
advanced technology nodes for embedded memory applications is their high, logic …

Effects of Charge Trapping on Memory Characteristics for HfO2-Based Ferroelectric Field Effect Transistors

J Wang, J Bi, Y Xu, G Niu, M Liu, V Stempitsky - Nanomaterials, 2023 - mdpi.com
A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-
based ferroelectric field effect transistors (FeFETs) will permit the design of program and …

Critical importance of nonuniform polarization and fringe field effects for scaled ferroelectric finfet memory

G Pahwa, S Salahuddin, C Hu - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory
technology that can offer ultra-scalability, fast operation, and reduced power consumption …

Optimizing De-trap Pulses in Gate-injection Type Ferroelectric NAND Cells to Minimize Read After Write Delay Issue

G Kim, H Choi, H Cho, S Lee, H Shin… - IEEE Electron …, 2024 - ieeexplore.ieee.org
The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS)
gate stacks, leverages both charge trapping and polarization (△ P) switching to achieve a …

Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications

D Das, H Park, Z Wang, C Zhang… - 2024 8th IEEE …, 2024 - ieeexplore.ieee.org
We experimentally demonstrate a novel gate stack engineering technique by introducing a
Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing …

New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface …

C Su, Z Liang, Z Fu, S Xu, K Wang, P Cai… - … 2023-IEEE 53rd …, 2023 - ieeexplore.ieee.org
The read current margin and memory window (MW) of HfO 2-based ferroelectric FET
(FeFET) are comprehensively re-evaluated by considering the impacts of the ferroelectric …

Disturb and its mitigation in Ferroelectric Field-Effect Transistors with Large Memory Window for NAND Flash Applications

P Venkatesan, C Park, T Song… - IEEE Electron …, 2024 - ieeexplore.ieee.org
We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-
engineered gate stacks. We demonstrate that integrating a dielectric Al 2 O 3 layer within the …

Plasma-Enhanced Atomic Layer Deposition Based Ferroelectric Field-Effect Transistors

C Park, PV Ravindran, D Das… - IEEE Journal of the …, 2024 - ieeexplore.ieee.org
The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition
of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up …

New Insight into Impacts from Read Cycle Number and Voltage Sweeping Direction on Memory Window of Ferroelectric Fet

C Su, Z Fu, S Xu, R Huang… - 2024 Conference of …, 2024 - ieeexplore.ieee.org
In this work, impacts from cycle number and direction of sweep voltage on electrical
characteristics of ferroelectric FET (FeFET) during readout are investigated. Considering …