An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …

5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …

This article presents a fully integrated stand-alone narrowband Internet-of-Things (NB-IoT)
and global navigation satellite system (GNSS) system-on-chip (SoC). It aims for an all-in-one …

This paper presents a second-order voltage-controlled oscillator (VCO)-based front-end for
the direct digitization of biopotential signals. This work addresses the non-linearity of VCO …

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often
limits the performance of such systems. Hence, a deep understanding of how oscillator …