In this work, we propose SVR-NoC, a learning-based support vector regression (SVR)
model for evaluating Network-on-Chip (NoC) latency performance. Different from the state-of …

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support
vector regression (SVR). More specifically, based on the application communication …

With the success of deep learning, there have been numerous efforts to build hardware for it.
One approach that is gaining momentum is neuromorphic computing with spiking neural …

In this work, we propose a new, accurate, and comprehensive analytical model for Network-
on-Chip (NoC) performance analysis. Given the application communication graph, the NoC …

In this survey, we review several approaches for predicting performance of Network-on-Chip
(NoC)-based multicore systems, starting from the traffic models to the complex NoC models …

Abstract The popularity of Machine Learning (ML) has extended to numerous disciplines,
including the domain of Network-on-chips (NoCs), leading to a consequential impact …

We introduce a novel evaluation methodology to analyze the delay of a wormhole routing
based NoC with variable link capacities and a variable number of virtual channels per link …

Analytical models used for latency estimation of Network-on-Chip (NoC) are not producing
reliable accuracy. This makes these analytical models difficult to use in optimization of …

In this paper, we propose a new fault-tolerant and congestion-aware adaptive routing
algorithm for Networks-on-Chip (NoCs). The proposed algorithm is based on the ball and …

Network-on-Chip (NoC) is a communication subsystem which has been widely utilized in
many-core processors and system-on-chips in general. In this paper, we focus on a Round …