This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS
technology. The latch comprises three interlocked single-node-upset-resilient cells and each …

Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy
a substantial proportion of chip area and consume significant amounts of power. This paper …

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly
susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU) …

This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch
to meet the high-robustness requirement of the applications used in a harsh radiation …

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch,
featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element …

This brief presents a double-node upset (DNU) self-recoverable latch design for high
performance and low power application. The latch is mainly constructed from eight mutually …

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation
induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node …

With continuous advancement in technology, latches have become highly susceptible to
radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the …

To meet the requirements of both high reliability and low power in low-orbit aerospace
applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable …

This paper presents a single event upset (SEU) resilient, single event transient (SET)
filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial …