Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
Aging mitigation in memory arrays using self-controlled bit-flipping technique
With CMOS technology downscaling into the nanometer regime, the reliability of SRAM
memories is threatened by accelerated transistor aging mechanisms such as Bias …
memories is threatened by accelerated transistor aging mechanisms such as Bias …
A survey on impact of transient faults on bnn inference accelerators
N Khoshavi, C Broyles, Y Bi - arXiv preprint arXiv:2004.05915, 2020 - arxiv.org
Over past years, the philosophy for designing the artificial intelligence algorithms has
significantly shifted towards automatically extracting the composable systems from massive …
significantly shifted towards automatically extracting the composable systems from massive …
Fundamentals, modeling, and application of magnetic tunnel junctions
Aggressive Metal Oxide Semiconductor (MOS) technology scaling in digital circuits has
resulted in important challenges including a significant increase in leakage currents, short …
resulted in important challenges including a significant increase in leakage currents, short …
Compression or corruption? a study on the effects of transient faults on bnn inference accelerators
N Khoshavi, C Broyles, Y Bi - 2020 21st International …, 2020 - ieeexplore.ieee.org
Over past years, the philosophy for designing the artificial intelligence algorithms has
significantly shifted towards automatically extracting the composable systems from massive …
significantly shifted towards automatically extracting the composable systems from massive …
A low area overhead NBTI/PBTI sensor for SRAM memories
Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale
technologies. BTI gradually increases the absolute value of threshold voltage (V th) of MOS …
technologies. BTI gradually increases the absolute value of threshold voltage (V th) of MOS …
Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective
M Hossain, MA Chowdhury… - … on Quality Electronic …, 2024 - ieeexplore.ieee.org
Hardware-based acceleration approaches for Machine Learning (ML) workloads have been
embracing the significant potential of post-CMOS switching devices to attain reduced …
embracing the significant potential of post-CMOS switching devices to attain reduced …
On microarchitectural mechanisms for cache wearout reduction
Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main
deleterious effects that increase a transistor's threshold voltage over the lifetime of a …
deleterious effects that increase a transistor's threshold voltage over the lifetime of a …
Bias temperature instability mitigation via adaptive cache size management
N Rohbani, M Ebrahimi, SG Miremadi… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales.
The main impact of BTI on SRAM memory cells is the degradation of the static noise margin …
The main impact of BTI on SRAM memory cells is the degradation of the static noise margin …
S-Tune: SOT-MTJ manufacturing parameters tuning for securing the next generation of computing
Hardware-based acceleration approaches for Machine Learning (ML) workloads have been
embracing the significant potential of post-CMOS switching devices to attain reduced …
embracing the significant potential of post-CMOS switching devices to attain reduced …