thin-film transistors (TFTs) for highly sensitive biosensing applications: a review

A Kumar, AK Goyal, N Gupta - … Journal of Solid State Science and …, 2020 - iopscience.iop.org
This review manuscript presents Thin-Film Transistors (TFTs) for various highly sensitive
biosensing applications. A low-cost, highly sensitive, early-stage diagnostic bio-sensing …

Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate all around (GS-GAA) FinFET

B Kumar, R Chaujar - Silicon, 2021 - Springer
This work presents the analog and RF performance evaluation of Junctionless Accumulation
Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have …

Influence of gate and channel engineering on multigate MOSFETs-A review

R Ramesh - Microelectronics journal, 2017 - Elsevier
The design of CMOS circuits using nanoscale MOSFET has become very difficult nowadays
as device modeling faces new challenges such as short channel effects and mobility …

TCAD temperature analysis of gate stack gate all around (GS-GAA) FinFET for improved RF and wireless performance

B Kumar, R Chaujar - Silicon, 2021 - Springer
In this article, we investigated the impact of temperature variation on DC, analog, RF, and
wireless performance of Gate Stack Gate All Around (GS-GAA) FinFET using SILVACO Atlas …

TCAD RF performance investigation of transparent gate recessed channel MOSFET

A Kumar, N Gupta, R Chaujar - Microelectronics Journal, 2016 - Elsevier
In this paper, analog/RF performance and small signal behavior of Transparent Gate
Recessed Channel (TGRC) MOSFET has been investigated in terms of transconductance …

Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications

A Kumar, MM Tripathi, R Chaujar - Superlattices and Microstructures, 2018 - Elsevier
In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-
Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm …

Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design

N Gupta, A Kumar - Applied Physics A, 2021 - Springer
In this work, inclusion of high-k spacer on symmetric underlap S/D junctionless silicon
nanowire (SiNW) MOSFET is studied with an aim to analyze more realistic estimation of …

Ambipolarity suppression of a double gate tunnel FET using high-k drain dielectric pocket

S Panda, B Jena, S Dash - ECS Journal of Solid State Science …, 2022 - iopscience.iop.org
The paper investigates the impact of placing a high-k dielectric pocket (DP) region in the
drain of a double gate silicon TFET. The sheer existence of the high-k DP reduces the …

Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

A Kumar - Superlattices and Microstructures, 2017 - Elsevier
This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate
length (LG) shrinking on analog and linearity performance of Transparent Gate Recessed …

Numerical simulation of analog metrics and parasitic capacitances of GaAs GS-GAA FinFET for ULSI switching applications

B Kumar, R Chaujar - The European Physical Journal Plus, 2022 - Springer
This paper explores the efficacy of Gallium Arsenide (GaAs) as a fin material on the analog
metrics and parasitic capacitances of Gate Stack Gate-All-Around (GS-GAA) FinFET …