Extended-source double-gate tunnel FET with improved DC and analog/RF performance

T Joshi, Y Singh, B Singh - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
In this article, we propose an extended-source double-gate tunnel field-effect transistor
(ESDG-TFET) to enhance the dc and analog/RF performance. The source of an ESDG-TFET …

Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application

MRU Shaikh, SA Loan - IEEE Transactions on Electron …, 2019 - ieeexplore.ieee.org
In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-
gate tunnel fieldeffect transistor (TFET). The proposed device employs a lateral dual source …

[PDF][PDF] Design and analysis of hetero dielectric dual material gate underlap spacer tunnel field effect transistor

S Howldar, B Balaji, K Srinivasa Rao - International Journal of Engineering …, 2023 - ije.ir
This paper presents a design and analysis of a Hetero Dielectric Dual Material Gate
Underlap Spacer Tunnel Field Effect Transistor, aiming to enhance device performance and …

A comparative analysis of cavity positions in charge plasma based tunnel FET for biosensor application

A Kumar, S Kale - IETE Journal of Research, 2024 - Taylor & Francis
This work reports a comparative analysis of different cavity positions in Charge Plasma-
based Tunnel Field Effect Transistor (CP TFET) for Biosensor Application. In CP TFET, we …

Noise behavior of vertical tunnel FETs under the influence of interface trap states

VD Wangkheirakpam, B Bhowmick… - Microelectronics …, 2021 - Elsevier
A detailed analysis of low frequency noise behavior of two different vertical TFETs namely
n​+​ pocket VTFET and dual MOS capacitor (D-MOS) VTFET is presented in this work …

Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor

P Kwatra, SV Singh, K Nigam - Microelectronics Reliability, 2023 - Elsevier
Tunnel field effect transistors (TFETs) offer advantage of robustness against short channel
effects. However, reliability issues caused by interface trap charges (ITCs) generated during …

Investigating a dual MOSCAP variant of line-TFET with improved vertical tunneling incorporating FIQC effect

M Ehteshamuddin, SA Loan, AG Alharbi… - … on Electron Devices, 2019 - ieeexplore.ieee.org
In this article, we investigate a variant of the line-tunnel FET employing dual MOS-capacitor
(MOSCAP) extensions incorporating field-induced quantum confinement (FIQC). Unlike …

Investigation of electrical parameters and temperature analysis of a dual-metal DG PNPN TFET with extended source

K Baruah, S Baishya - Engineering Research Express, 2023 - iopscience.iop.org
In this article, a dual-metal double-gate extended-source PNPN tunnel-FET (DG-ES-DMG
TFET) is proposed and investigated. The performance of conventional double-gate PNPN …

Investigation of a dual MOSCAP TFET with improved vertical tunneling and its near-infrared sensing application

VD Wangkheirakpam, B Bhowmick… - Semiconductor …, 2020 - iopscience.iop.org
In this work, a δ-doped dual MOS-capacitor (MOSCAP)(D-MOS) tunnel field effect transistor
is proposed and investigated. The investigation has been carried out by varying the mole …

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

M Elnaggar, A Shaker, M Fedawy - Semiconductor Science and …, 2019 - iopscience.iop.org
In this paper, we have investigated the effect of gate underlap, while using semiconducting
silicide material as a source region, on the ambipolar and high-frequency performance of …