Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer
technologies. Among various design implementation schemes, standard cell ASICs offer the …
technologies. Among various design implementation schemes, standard cell ASICs offer the …
Gate-length biasing for runtime-leakage control
Leakage power has become one of the most critical design concerns for the system level
chip designer. While lowered supplies (and consequently, lowered threshold voltage) and …
chip designer. While lowered supplies (and consequently, lowered threshold voltage) and …
Real-time facial animation based upon a bank of 3D facial expressions
C Kouadio, P Poulin… - … Computer Animation'98 …, 1998 - ieeexplore.ieee.org
We present an animation system that captures live facial expressions from a performance
actor and uses them to animate in real time a synthetic character. Our approach is based …
actor and uses them to animate in real time a synthetic character. Our approach is based …
Physical synthesis methodology for high performance microprocessors
YH Chan, P Kudva, L Lacey, G Northrop… - Proceedings of the 40th …, 2003 - dl.acm.org
Integrated logic synthesis and physical design (physical synthesis) continues to play a very
important role in high performance microprocessor design methodologies. In this paper, we …
important role in high performance microprocessor design methodologies. In this paper, we …
A practical transistor-level dual threshold voltage assignment methodology
Leakage power has become one of the most critical design concerns for the system-level
chip designer. Multi-threshold techniques have been used to reduce runtime leakage power …
chip designer. Multi-threshold techniques have been used to reduce runtime leakage power …
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
BW Curran, YH Chan, PT Wu… - IBM Journal of …, 2002 - ieeexplore.ieee.org
The IBM eServer z900 microprocessor is a seventh-generation zSeries™(formerly S/390®)
CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm …
CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm …
There is life left in ASICs
L Stok, J Cohn - Proceedings of the 2003 international symposium on …, 2003 - dl.acm.org
Standard cells have long been an excellent abstraction of technology. ASIC design styles
allowed logic designers to very rapidly take advantage of major advantages in silicon …
allowed logic designers to very rapidly take advantage of major advantages in silicon …
Generalizing: is it possible to create all-purpose simulations?
GP Rioux, RE Nance - Proceedings of the Winter Simulation …, 2002 - ieeexplore.ieee.org
The title poses the essential question addressed: is it possible to construct simulations that
permit use in application domains with widely ranging objectives? The question is raised in …
permit use in application domains with widely ranging objectives? The question is raised in …
Cell uniquification
AI Reis - US Patent 8,214,787, 2012 - Google Patents
Methods reduce the number of newly created cells when creating new cells to optimize a
design. Cells are created to optimize a design, but neighbor cells fitting a distribution of drive …
design. Cells are created to optimize a design, but neighbor cells fitting a distribution of drive …
Enriching a cell library
OC Andersen - US Patent 8,607,185, 2013 - Google Patents
Methods are used to enrich a cell library in such a way to provide a nearly continuous choice
of cells to implement a circuit design. The emphasis of the design method is on automatic …
of cells to implement a circuit design. The emphasis of the design method is on automatic …