A design technique for energy reduction in NORA CMOS logic

K Limniotis, Y Tsiatouhas, T Haniotakis… - … on Circuits and …, 2006 - ieeexplore.ieee.org
In this work, a design technique to reduce the energy consumption in NO RAce (NORA)
circuits is presented. The technique is based on a unidirectional switch topology combined …

Design of Low-Power Transceiver for Memory Interface

박정훈 - 2023 - s-space.snu.ac.kr
This thesis presents design techniques for low-power transceivers for memory interfaces. In
terms of two trends to improve the bandwidth of the memory interface, fast-and-narrow and …

[PDF][PDF] A charge recycling differential noise immune perceptron

J Nyathi, V Beiu, S Tatapudi… - Proc. Intl. Joint Conf …, 2004 - researchgate.net
This paper proposes a new differential neural inspired gate with improved noise immunity.
The charge recycling differential noise-immune threshold logic (CRD-NTL) perceptron is …

[PDF][PDF] A comparative study of adiabatic circuit techniques towards asynchronous adiabatic systems

M Arsalan - 2004 - repository.library.carleton.ca
To keep up with the recent trend towards portable and handheld computing, designers are
forced to explore some means to increase the battery life of such devices. In this scenario …

Review of charge-sharing logic circuits

M Arsalan, M Shams - Canadian Conference on Electrical and …, 2004 - ieeexplore.ieee.org
Energy efficient circuit design is one of the crucial requirements for future consumer devices,
especially portable products and computers. Conventional dynamic circuit techniques are …

[引用][C] An Integrated Low-Power 14-bit Analog-to-Digital Converter for a MEMS Capacitive Sensor

JJ Cantrell - 2003 - University of California, Los Angeles

[引用][C] FEMTO JOULE SWITCHING: REVIEW OF A SELECT, LOW ENERGY DESIGN STYLES FOR THE NANO ERA

J Nyathi, V Beiu, S Aunet