Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet
the growing complexity of embedded applications with increasing computation parallelism …

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to
compete with the power dissipated by the other elements of the communication subsystem …

Many state-of-the-art approaches to power minimisation in Networks-on-Chip (NoC) are
based on the reduction of the communication paths taken by packets over the interconnect …

During the last two decades, the advent of very deep sub-micron and nanometric
technologies has increased the criticality of the on-chip interconnect architecture. Today …

In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant
research solution to on-chip multiprocessor-based real-time applications. As the number of …

Emerging on-chip communication technologies, like wireless networks-on-chip (WiNoCs),
have been recently proposed as candidate solutions for addressing the scalability limitations …

This paper presents the design and the characterization in nanoscale CMOS technology of a
Network Interface (NI) for on-chip communication infrastructure with hardware support of …

Soft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause
hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error …

In a multi/many-core system, the network-on-chip (NoC)-based communication backbone is
responsible for a relevant fraction of the overall energy budget. Reducing the voltage swing …

Abstract In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect
design are to meet the performance, power consumption requirements of the SoC and to …