Characterization of single-event upsets induced by high-LET heavy ions in 16-nm bulk FinFET SRAMs
C Yaqing, H Pengcheng, S Qian, L Bin… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
For advanced technology nodes, the static random access memories (SRAMs) are highly
vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by …
vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by …
14 nm pFinFET 器件抗单粒子辐射的加固方法
史柱， 王斌， 杨博， 赵雁鹏， 惠思源… - 北京航空航天大学学报, 2022 - bhxb.buaa.edu.cn
为探究先进互补金属氧化物半导体(CMOS) 工艺在空间应用中的可靠性问题, 研究14 nm
工艺下P 型沟道鳍式场效应晶体管(pFinFET) 器件中的抗单粒子瞬态(SET) 加固策略 …
工艺下P 型沟道鳍式场效应晶体管(pFinFET) 器件中的抗单粒子瞬态(SET) 加固策略 …
Single-event radiation hardening method for 14 nm pFinFET device
Z SHI, B WANG, B YANG, Y ZHAO, S HUI… - 北京航空航天大学 …, 2022 - bhxb.buaa.edu.cn
In order to investigate the reliability of advanced complementary metal-oxide-semiconductor
(CMOS) processes for space applications, a hardening strategy against single-event …
(CMOS) processes for space applications, a hardening strategy against single-event …
Single-event upset responses of dual-and triple-well D flip-flop designs in 7-nm bulk FinFET technology
Triple-well designs provide excellent noise isolation in mixed-signal circuits. But the
presence of deep-n-well significantly affects Single-Event (SE) response of these circuits …
presence of deep-n-well significantly affects Single-Event (SE) response of these circuits …