A 21.8–41.6-GHz Low Jitter and High FoM $ _ {\bm {j}} $ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller
In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-
locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM) is proposed …
locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM) is proposed …
A “2 1” Cores Triple-Mode Oscillator
S Deng, X Yi, P Qin, T Xu, C Wan, X Luo… - … on Circuits and …, 2024 - ieeexplore.ieee.org
This paper proposes a millimeter-wave (mmW) oscillator with “2 1” cores and triple operation
modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a …
modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a …
An octave tuning range quad-core VCO using a multi-mode resonator
S Duan, Z Li, Y Wu, D Dong, X He, J Leng… - AEU-International Journal …, 2024 - Elsevier
This paper presents a novel multi-core multi-mode electric-magnetic (EM) mixed-coupling
voltage-controlled oscillator (VCO), achieving wide tuning range and phase noise …
voltage-controlled oscillator (VCO), achieving wide tuning range and phase noise …
[HTML][HTML] A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning
B Kang, Y Kim, H Son, S Kim - Electronics, 2024 - mdpi.com
This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL)
architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to …
architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to …
A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators
D Sun, R Wang, F Bu, Y Gao, X Zhao, R Ding… - Microelectronics …, 2024 - Elsevier
This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked
loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the …
loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the …
A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch
X Kong, D Qiu, M Jian, C Guo… - 2023 IEEE 15th …, 2023 - ieeexplore.ieee.org
This paper proposed a dual-core quad-mode with re-configurable magnetic coupling mode
and negative-resistive mode switch VCO implemented with 65nm CMOS technology. By …
and negative-resistive mode switch VCO implemented with 65nm CMOS technology. By …
A 7.2 G-16GHz ADPLL based on a single-core dual-mode DCO
N Zhang, S Zhang, F Yang, Y Wang… - 2024 IEEE European …, 2024 - ieeexplore.ieee.org
This work proposed a 75.9% wide frequency tuning range (FTR), low-jitter All Digital Phase
Locked Loop (ADPLL) based on a new single-core dual-mode digital controlled oscillator …
Locked Loop (ADPLL) based on a new single-core dual-mode digital controlled oscillator …