Reliability-aware resource management in multi-/many-core systems: A perspective paper
With the advancement of technology scaling, multi/many-core platforms are getting more
attention in embedded systems due to the ever-increasing performance requirements and …
attention in embedded systems due to the ever-increasing performance requirements and …
Aging resilience and fault tolerance in runtime reconfigurable architectures
Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs)
allow areaand power-efficient acceleration of complex applications. However, being …
allow areaand power-efficient acceleration of complex applications. However, being …
Exploiting heterogeneity for aging-aware load balancing in mobile platforms
The pervasiveness of heterogeneous multiprocessors (HMP) in the mobile domain enables
more energy efficient systems. However, current approaches to exploit the energy efficiency …
more energy efficient systems. However, current approaches to exploit the energy efficiency …
SENSIBle: A highly scalable sensor design for path-based age monitoring in FPGAs
Z Ghaderi, M Ebrahimi, Z Navabi… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
This paper proposes a highly scalable sensor design for late transition detection in FPGA
based platforms. Transition delays occur because of aging mechanisms such as Biased …
based platforms. Transition delays occur because of aging mechanisms such as Biased …
STABLE: Stress-aware boolean matching to mitigate BTI-induced SNM reduction in SRAM-based FPGAs
Z Ghaderi, N Bagherzadeh… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Biased-Temperature-Instability (BTI) aging mechanism reduces Static-Noise-Margin (SNM)
of SRAM cells. This leads to a higher Soft-Error-Rate (SER), lower reliability, and lower …
of SRAM cells. This leads to a higher Soft-Error-Rate (SER), lower reliability, and lower …
AROMa: aging-aware deadlock-free adaptive routing algorithm and online monitoring in 3D NoCs
Z Ghaderi, A Alqahtani… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve
area, performance, power, and scalability of many-core systems. However, reliability issue …
area, performance, power, and scalability of many-core systems. However, reliability issue …
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
Abstract Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based
systems. It can also be used for the mitigation of aging-related permanent faults by …
systems. It can also be used for the mitigation of aging-related permanent faults by …
Using novel configuration techniques for accelerated FPGA aging
T Gaskin, H Cook, W Stirk, R Lucas… - … Conference on Field …, 2020 - ieeexplore.ieee.org
In this work we demonstrate a novel method of accelerating FPGA aging by configuring the
FPGA to implement thousands of short circuits, resulting in high on-chip currents and …
FPGA to implement thousands of short circuits, resulting in high on-chip currents and …
Inducing non-uniform FPGA aging using configuration-based short circuits
H Cook, J Arscott, B George, T Gaskin… - ACM Transactions on …, 2022 - dl.acm.org
This work demonstrates a novel method of accelerating FPGA aging by configuring FPGAs
to implement thousands of short circuits, resulting in high on-chip currents and temperatures …
to implement thousands of short circuits, resulting in high on-chip currents and temperatures …
Low latency reconfiguration mechanism for fine-grained processor internal functional units
RS Ferreira, J Nolte - 2019 IEEE Latin American Test …, 2019 - ieeexplore.ieee.org
The strive for performance, low power consumption, and less chip area have been
diminishing the reliability and the time to fault occurrences due to wear out of electronic …
diminishing the reliability and the time to fault occurrences due to wear out of electronic …