Abstract Model checking is an automatic technique for verifying finite-state reactive systems,
such as sequential circuit designs and communication protocols. Specifications are …

Many different methods have been devised for automatically verifying finite state systems by
examining state-graph models of system behavior. These methods all depend on decision …

We describe a method for using abstraction to reduce the complexity of temporal-logic
model checking. Using techniques similar to those involved in abstract interpretation, we …

The phrase model checking refers to algorithms for exploring the state space of a transition
system to determine if it obeys a specification of its intended behavior. These algorithms can …

This paper describes a new symbolic model checker, called NuSMV, developed as part of a
joint project between CMU and IRST. NuSMV is the result of the reengineering …

In this paper we present theory and experimental results on Algebraic Decision Diagrams.
These diagrams extend BDDs by allowing values from an arbitrary finite domain to be …

This paper describes NuSMV, a new symbolic model checker developed as a joint project
between Carnegie Mellon University (CMU) and Istituto per la Ricerca Scientifica e …

We describe a technique for verifying the control logic of pipelined microprocessors. It
handles more complicated designs, and requires less human intervention, than existing …

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is
modified to represent state graphs using binary decision diagrams (BDD's) and partitioned …

In this doctoral dissertation, we study three basic problems in machine learning and two new
hypothesis spaces with corresponding learning algorithms. The problems we investigate …