Hardware efficient approximate multiplier architecture for image processing applications
S Chandaka, B Narayanam - Journal of Electronic Testing, 2022 - Springer
In this research paper, approximate multipliers are designed to reduce the computational
time and power delay product. However, there is a high possibility to further optimize the …
time and power delay product. However, there is a high possibility to further optimize the …
Error-efficient approximate multiplier design using rounding based approach for image smoothing application
EJ Rao, P Samundiswary - Journal of Electronic Testing, 2021 - Springer
We propose a novel, error-efficient approximate multiplier (EEAM), which is based on a
rounding-based approach (RBA). Multiplication is performed using rounding, shift, and add …
rounding-based approach (RBA). Multiplication is performed using rounding, shift, and add …
Area and delay optimized two step binary adder using carry substitution algorithm for FIR filter
VD Christilda, A Milton - Analog Integrated Circuits and Signal Processing, 2022 - Springer
Adders are used to design the basic building blocks of very large scale integrated systems.
Most of the computer arithmetic applications need highest degree of accuracy with good …
Most of the computer arithmetic applications need highest degree of accuracy with good …
Reconfigurable carry look-ahead adder trading accuracy for energy efficiency
The modern portable devices exhibiting multimedia applications demand higher energy
efficient signal processing due to limited battery size. The approximate adders have shown a …
efficient signal processing due to limited battery size. The approximate adders have shown a …
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application
DT Raju, YS Rao - Journal of Electronic Testing, 2022 - Springer
Error-Tolerant applications regularly accomplish more data adaption. Approximate
computing is one of the optimum strategies for data manipulation in several Error-Tolerant …
computing is one of the optimum strategies for data manipulation in several Error-Tolerant …
High Performance 32 bit Dadda Multiplier Using EDA
MVS Nandam, S Alluri - 2020 7th International Conference on …, 2020 - ieeexplore.ieee.org
The adder is the basic hardware unit of arithmetic operation. Thus output adder influences
the actual performance of the system CSA which is Carry Select Adder regularly used for …
the actual performance of the system CSA which is Carry Select Adder regularly used for …