A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

CA Prete, G Prina, L Ricciardi - IEEE Transactions on Parallel …, 1995 - ieeexplore.ieee.org
We describe a simulator which emulates the activity of a shared memory, common bus
multiprocessor system with private caches. Both kernel and user program activities are …

Hardware approaches to cache coherence in shared-memory multiprocessors. 2

M Tomasevic, V Milutinovic - IEEE Micro, 1994 - ieeexplore.ieee.org
Improving performance and scalability in shared-memory multiprocessors requires an
appropriate solution to the well-known cache coherence problem. Hardware schemes …

[图书][B] Computer architecture

G Blanchet, B Dupouy - 2013 - books.google.com
This book lays out the concepts necessary to understand how a computer works. For
reasons of clarity, the authors have deliberately chosen examples that apply to machines …

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

R Giorgi, CA Prete - IEEE Transactions on Parallel and …, 1999 - ieeexplore.ieee.org
In high-performance general-purpose workstations and servers, the workload can be
typically constituted of both sequential and parallel applications. Shared-bus shared …

[PDF][PDF] Coherence protocols for bus-based and scalable multiprocessors, internet, and wireless distributed computing environments: A survey

JP Sustersic, AR Hurson - Advances in Computers, 2003 - scholar.archive.org
Caching has been widely used in many diverse computer applications to improve
performance. Although these applications often utilize diverse platforms due to their inherent …

Cachesim: A graphical software environment to support the teaching of computer systems with cache memories

CA Prete - Software Engineering Education: 7th SEI CSEE …, 1994 - Springer
We present an educational software package (Cachesim) used as a teaching tool for
studying and analysing computers with cache memories. Cachesim allows students to …

Simulation study of memory performance of SMP multiprocessors running a TPC-W workload

P Foglia, R Giorgi, CA Prete - IEE Proceedings-Computers and Digital …, 2004 - IET
The infrastructure to support electronic commerce is one of the areas where more
processing power is needed. A multiprocessor system can offer advantages for running …

Fine-grain design space exploration for a cartographic SoC multiprocessor

A Bechini, P Foglia, CA Prete - ACM SigArch Computer Architecture …, 2003 - dl.acm.org
Traditionally, in the field of embedded systems low power consumption and low cost have
been always regarded as stringent specification constraints. In recent years, high …

Effective use of memory bus in a multiprocessing environment by controlling end of data intervention by a snooping cache

SA Shah - US Patent 5,586,298, 1996 - Google Patents
(57) ABSTRACT A cache control circuit reduces the number of accesses to main memory in
a multiprocessing system. The circuit allows a cache memory associated with one Central …

Evaluating optimizations for multiprocessors e-commerce server running TPC-W workload

P Foglia, R Giorgi, CA Prete - Proceedings of the 34th Annual …, 2001 - ieeexplore.ieee.org
The performance of an electronic commerce server, ie a system running electronic
commerce applications is evaluated in the case of shared-bus multiprocessor architecture …