Locality transformations and prediction techniques for optimizing multicore memory performance

AHA Badawy - 2013 - search.proquest.com
Abstract Chip Multiprocessors (CMPs) are here to stay for the foreseeable future. In terms of
programmability of these processors what is different from legacy multiprocessors is that …

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs

M Ortín-Obón, D Suárez-Gracia… - Journal of Parallel and …, 2016 - Elsevier
Abstract Networks on Chip (NoCs) have a large impact on system performance, area, and
energy. NoCs convey request and response messages among cores following the message …

[PDF][PDF] Reactive Circuits: Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs

M Ortın-Obón, D Suárez-Gracia, M Villarroya-Gaudó… - academia.edu
Abstract Networks on Chip (NoCs) have a large impact on system performance, area, and
energy. NoCs convey request and response messages among cores following the message …

Switch-based packing technique to reduce traffic and latency in token coherence

B Cuesta, A Robles, J Duato - Journal of Parallel and Distributed …, 2012 - Elsevier
Token Coherence is a cache coherence protocol able to simultaneously capture the best
attributes of traditional protocols: low latency and scalability. However it may lose these …

[PDF][PDF] Networks-on-Chip: from the Optimization of Traditional Electronic NoCs to the Design of Emerging Optical NoCs

MO Obón - 2016 - webdiis.unizar.es
Nowadays, a single chip may contain multiple processors and a significant amount of
memory. A popular trend consists of interconnecting several nodes, each of them with a core …

[PDF][PDF] A Complete Bibliography of ACM Transactions on Architecture and Code Optimization

NHF Beebe - 2024 - netlib.sandia.gov
A Complete Bibliography of ACM Transactions on Architecture and Code Optimization Page
1 A Complete Bibliography of ACM Transactions on Architecture and Code Optimization …